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51408 ti im / 82907 ti im 20060927-s00005 no.a0898-1/16 specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. la74308lp overview the la74308lp is a speaker amp and mi c amp built-in audio interface for dsc. it incorporates an 8/16khz trap and supports codecs with a sampling rate of 8khz or 16khz. features ? three-wire type serial communication ? mic amp ? mic power supply incorporated (with built-in pull-up resistor) ? alc amp ? 4th order lpf + trap (compatible with rec/pb changeover, trap frequency selectable from 8khz and 16khz) ? speaker amp (the beep signal can be mixed.) ? electronic volume (controlle d by serial communication) ? line output (with serial mute and mute transistor) ? standby control specifications maximum ratings at ta=25 c parameter symbol conditions ratings unit maximum supply voltage v cc max 5.0 v allowable power dissipation pd max ta 85 c * 500 mw operating temperature topr -10 to +85 c storage temperature tstg -55 to +150 c * printed circuit board mounting condition (40mm 50mm 0.8mm: glass epoxy) 2s2p (four layers printed circuit board) ordering number : ena0898a monolithic linear ic audio interface for dsc
la74308lp no.a0898-2/16 operating conditions at ta = 25 c parameter symbol conditions ratings unit v cc a 3.0 v recommended operating voltage v cc sp 3.3 v v cc aop 2.7 to 3.6 v allowable operating voltage range v cc spop take care not to exceed pd max. 2.7 to 3.6 v electrical characteristics at ta=25 c, v cc a=3.0v, v cc sp=3.3v, f=1khz, with the vref capacitance charging circuit in the off mode ratings parameter symbol conditions min typ max unit circuit current v cc a current dissipation at no signal 1 i cc a1 v cc a=3.0v:rec block(mic/alc/rec amp) power save mode 4.9 6.6 8.3 ma v cc a current dissipation at no signal 2 i cc a2 v cc a=3.0v, line/sp amp power save mode 6.2 8.3 10.4 ma v cc a standby current dissipation 1 i cc as1 v cc a=3.0v, during standby control v3=0v 1 a v cc a standby current dissipation 2 i cc as2 v cc a=3.0v, bias mode 800 a v cc sp current dissipation at no signal 1 i cc s1 v cc sp=3.3v, spk power on mode 1 2 4 ma v cc sp current dissipation at no signal 2 i cc s2 v cc sp=3.3v, spk power save mode 0.05 0.1 ma v cc sp standby current dissipation 1 i cc ss1 v cc sp=3.3v, during standby control (0v applied to pin 3) 9 a v cc sp standby current dissipation 2 i cc ss2 v cc sp=3.3v, bias mode 9 a rec output system rec reference output level vor alc in, v in =-53dbv -11 -9.5 -8 dbv rec reference output distortion hdr1 alc in, v in =-53dbv, thd: from 2nd to 5th harmonic 0.1 0.2 % alc characteristics alm alc in, v in =-20dbv -3 -1.8 dbv alc distortion almd alc in, v in =-20dbv, thd: from 2nd to 5th harmonic 0.3 1 % alc in max input level vinrmx alc in level at which rec output thd (from 2nd to 5th harmonic) becomes 3% or less. -7 dbv rec output noise voltage vnor alc in, no input, jis-a filter -70 -60 dbv line output system (line load = as measured at the 22k end) line reference output level vol pb in, v in =-17dbv -11 -9.5 -8 dbv line reference output distortion hdl pb in, v in =-17dbv, thd: from 2nd to 5th harmonic 0.1 0.2 % line reference output noise voltage vnol pb in, no input , jis-a filter -77 -69 dbv pb in max input level vinpmx pb in level at which line output thd (from 2nd to 5th harmonic) becomes 1% or less. -9 dbv line output frequency characteristics 1 feqp1 pb in, v in =-10dbv, comparison of f=3khz/1khz -3.5 -2 db line output frequency characteristics 2 feqp2 pb in, v in =-10dbv, comparison of f=4khz/1khz -10 -6 db line output frequency characteristics 3 feqp3 pb in, v in =-10dbv, comparison of f=8khz/1khz -55 -30 db sp output system (sp load = as measured at the 8 end) sp reference output level1 (vol.max) vosp1 pb in, v in =-17dbv, vol=max (evr data=31) -6 -3 0 dbv sp reference output distortion thdsp pb in, v in =-17dbv, vol=max, thd: from 2nd to 5th harmonic 0.4 1 % sp reference output level2 (vol.typ) vosp2 pb in, v in =-17dbv, vol=typ (evr data=14) -18 -12 -6 dbv sp reference output level3 (vol.min) vosp3 pb in, v in =-17dbv,vol=min (evr data=0) jis-a filter -80 -70 dbv sp reference output noise voltage vnosp pb in no input, vol= max, jis-a filter -70 -64 dbv sp maximum ratings output vomsp pb in, vol=max, level at which thd=10% 200 320 mw continued on next page.
la74308lp no.a0898-3/16 continued from preceding page. ratings parameter symbol conditions min typ max unit mic output system mic voltage gain vgmic mic in, v in =-36dbv 16 17 18 db mic output distortion hdmic mic in, v in =-36dbv, thd: from 2nd to 5th harmonic 0.05 0.1 % mic output noise voltage vnomic mi c in, no input, jis-a filter -94 -83 dbv mic in max input level vinmmx mic in level at which the mic output thd (from 2nd to 5th harmonic) becomes 3% or less. -25 dbv mic v cc output voltage vmic at 6.2k load 1.5 1.7 1.9 v control system serial clock frequency fclk 0.1 1 mhz serial input low level serlo 0 0.7 v serial input high level serhi 2.3 3.5 v package dimensions unit : mm (typ) 3321 sanyo : vqlp24(3.5x3.5) 0.85max 0.0nom 0.75 0.75 bottom view 3.5 0.35 0.35 0.2 3.5 0.4 top view top view 1 6 7 12 13 18 19 24
la74308lp no.a0898-4/16 description of the content of serial communication data no. parameter default lsb 0 line mute tr. 0:off, 1:on 1 1 vref capacitance charging circuit sw 0:off, 1:on 1 2 mic amp power sw 0:on, 1:off 1 3 alc amp power sw 0:on, 1:off 1 4 rec/pb changeover sw 0:pb, 1:rec 0 5 lpf characteristics (trap) c hangeover sw 0:16khz, 1:8khz 1 6 rec amp power sw 0:on, 1:off 1 7 line out power sw 0:on, 1:off 1 8 line mute sw 0:off, 1:on 1 9 spk power sw 0:on, 1:off 1 10 data=1 1 1 1 1 1:vol max 0 11 data=2 0 12 data=4 0 0 0 0 0:vol min (mute) 0 13 data=8 0 14 data=16 0 msb 15 bias mode 0:active mode, 1:bias mode 0 serial transmission timing ? f max (max clock frequency) 1.0mhz ? t wl (clock pulse width: low) 500ns or more ? t wh (clock pulse width: high) 500ns or more ? t cs (chip enable setup time) 500ns or more ? t ch (chip enable hold time) 500ns or more ? t ds (data setup time) 500ns or more ? t dh (data hold time) 500ns or more ? t wc (chip enable pulse width) 500ns or more ? v ih (high voltage lower limit) 2.3v to 3.5v ? v il (low voltage upper limit) 0.0v to 0.7v * evr setting (the numeral shown in the left is decimal. for characteristics, see p12.) f max t wh cs clock t cs t wl t ch data lsb t ds t dh msb t wc v il v ih v ih v il v ih v il
la74308lp no.a0898-5/16 power on reset condition (serial communication) the power on reset state covers a period up to the rise f of the second c.s. input after fall d of power on pulse c generated inside ic when the power is supplied and the standby control is canceled. e is the dummy communication. actually, because of delay of several hundreds ns in the ic, the first data condition begins in g and the normal serial communication condition begins after g . high period for about 2ms delay of several hundreds ns serial communication condition (first data hold) (first c.s.) dummy communication power supply h l standby control (pin 3) high to cancel standby h l power on pulse (signal inside ic) h l c d c.s. (pin 6) e f g h l h l power on reset (ic inside) power on reset (default) state data (pin 8) h l clock (pin 7) h l dummy data first data (second c.s.) first data communication
la74308lp no.a0898-6/16 bias mode canceling state (serial communication) the power on reset state from the bias mode covers the period from the rise of c.s c for communication of canceling of the bias mode to the second rise g of cs input after the fall e of power on pulse d generated inside ic. f is the dummy communication. actually, because of delay of several hundreds ns in the ic, the first data condition begins in h and the normal serial communication condition begins after h . h l h l h l d e f g h h l h l power on reset (ic inside) power on reset (default) state h l clock (pin 7) h l c high period for about 5
la74308lp no.a0898-7/16 electrical characteristi cs measurement method at ta=25 c, v cc a=3.0v, v cc sp=3.3v, f=1khz with the vref capacitance ch arging circuit in the off mode 15 bias mode 0:active 1:bias 0 0 0 1 0 0 0 1 0 0 0 0 0 0 14 evr16 data 0:off 1:on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 evr8 data 0:off 1:on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 evr4 data 0:off 1:on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 evr2 data 0:off 1:on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 evr1 data 0:off 1:on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 spk p sw 0:on 1:off 0 1 0 0 0 1 0 0 1 1 1 1 1 1 8 line mute 0:off 1:on 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 line p sw 0:on 1:off 0 1 0 0 0 0 0 0 1 1 1 1 1 1 6 rec p sw 0:on 1:off 1 0 0 0 1 1 1 1 0 0 0 0 0 0 5 lpf trap 0:16khz 1:8khz 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 rec /pb sw 0:pb 1:rec 0 1 0 0 0 0 0 0 1 1 1 1 1 1 3 alc p sw 0:on 1:off 1 0 0 0 1 1 1 1 0 0 0 0 0 0 2 mic p sw 0:on 1:off 1 0 0 0 1 1 1 1 0 0 0 0 0 0 1 vref charging sw 0:off 1:on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 serial control setting 0 line mute tr. 0:off 1:on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 standby pin voltage applied to pin 3 3.3v 3.3v 0v 3.3v 3.3v 3.3v 0v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v major conditions (for the serial control setting, see the table in the right) vref capacitance charging circuit in the off mode mic/alc/rec amp power save mode vref capacitance charging circuit in the off mode line/sp amp power save mode with the standby pin v3=0v bias mode vref capacitance charging circuit in the off mode spk power on mode vref capacitance charging circuit in the off mode spk power save mode with the standby pin v3=0v bias mode 400 to 20khz lpf used sw14=a, sw16=b 400 to 20khz lpf used, sw14=a sw16=b, thd: from 2nd to 5th harmonic 400 to 20khz lpf used, sw14=a, sw16=b 400 to 20khz lpf used, sw14=a sw16=b, thd: from 2nd to 5th harmonic 400 to 20khz lpf used, sw16=b pin 14 level at which pin 12 becomes thd = 3% from 2nd to 5th harmonic) jis-a filter used sw14=b, sw16=b output pin t11 t11 t11 t11 t22 t22 t22 t22 t12 t12 t12 t12 t12 t12 conditions v cc a=3.0v no input v cc a=3.0v no input v cc a=3.0v no input v cc a=3.0v no input v cc sp=3.3v no input v cc sp=3.3v no input v cc sp=3.3v no input v cc sp=3.3v no input v in =-53dbv f=1khz v in =-53dbv f=1khz v in =-20dbv f=1khz v in =-20dbv f=1khz f=1khz no input input pin t11 t11 t11 t11 t22 t22 t22 t22 t14 t14 t14 t14 t14 t14 symbol i cc a1 i cc a2 i cc as1 i cc as2 i cc s1 i cc s2 i cc ss1 i cc ss2 vor hdr1 alm almd vinrmx vnor no. circuit current 1 2 3 4 5 6 7 8 rec output system 9 10 11 12 13 14
la74308lp no.a0898-8/16 15 bias mode 0:active 1:bias 0 0 0 0 0 0 0 0 0 0 0 0 0 14 evr16 data 0:off 1:on 0 0 0 0 0 0 0 1 1 0 0 1 1 13 evr8 data 0:off 1:on 0 0 0 0 0 0 0 1 1 1 0 1 1 12 evr4 data 0:off 1:on 0 0 0 0 0 0 0 1 1 1 0 1 1 11 evr2 data 0:off 1:on 0 0 0 0 0 0 0 1 1 1 0 1 1 10 evr1 data 0:off 1:on 0 0 0 0 0 0 0 1 1 0 0 1 1 9 spk p sw 0:on 1:off 1 1 1 1 1 1 1 0 0 0 0 0 0 8 line mute 0:off 1:on 0 0 0 0 0 0 0 1 1 1 1 1 1 7 line p sw 0:on 1:off 0 0 0 0 0 0 0 1 1 1 1 1 1 6 rec p sw 0:on 1:off 1 1 1 1 1 1 1 1 1 1 1 1 1 5 lpf trap 0:16khz 1:8khz 1 1 1 1 1 1 1 1 1 1 1 1 1 4 rec /pb sw 0:pb 1:rec 0 0 0 0 0 0 0 0 0 0 0 0 0 3 alc p sw 0:on 1:off 1 1 1 1 1 1 1 1 1 1 1 1 1 2 mic p sw 0:on 1:off 1 1 1 1 1 1 1 1 1 1 1 1 1 1 vref charging sw 0:off 1:on 0 0 0 0 0 0 0 0 0 0 0 0 0 serial control setting 0 line mute tr. 0:off 1:on 0 0 0 0 0 0 0 0 0 0 0 0 0 standby pin voltage applied to pin 3 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v 3.3v major conditions (for the serial control setting, see the table in the right) 400 to 20khz lpf used sw10=a, sw16=a 400 to 20khz lpf used, sw10=a sw16=a, thd: from 2nd to 5th harmonic jis-a filter used, sw10=b, sw16=a 400 to 20khz lpf used, sw10=a, pin 10 level at which pin 5 becomes thd = 3% (from 2nd to 5th harmonic) f=3khz/1khz level ratio sw10=a, sw16=a f=4khz/1khz level ratio sw10=a, sw16=a f=8khz/1khz level ratio sw10=a, sw16=a 400 to 20khz lpf used vol.=max (evr data=31) 400 to 20khz lpf used, vol.=max thd: from 2nd to 5th harmonic 400 to 20khz lpf used vol.=typ (evr data=14) jis-a filter used vol.=min (evr data=0) jis-a filter used vol.=max (evr data=31) 400 to 20khz lpf used vol.=max (evr data=31) level at which vol.=max and thd=10% (from 2nd to 5th harmonic) output pin t5 t5 t5 t5 t5 t5 t5 t21 t23 t21 t23 t21 t23 t21 t23 t21 t23 t21 t23 conditions v in =-17dbv f=1khz v in =-17dbv f=1khz no input f=1khz v in =-10dbv f=3khz v in =-10dbv f=4khz v in =-10dbv f=8khz v in =-17dbv f=1khz v in =-17dbv f=1khz v in =-17dbv f=1khz v in =-17dbv f=1khz no input f=1khz input pin t10 t10 t10 t10 t10 t10 t10 t10 t10 t10 t10 t10 t10 symbol vol1 hdl vnol vinpmx feqp1 feqp2 feqp3 vosp1 thdsp vosp2 vosp3 vnosp vossp no. line output system 15 16 17 18 19 20 21 spk output system (spk end: measured with 8 ) 22 23 24 25 26 27
la74308lp no.a0898-9/16 15 bias mode 0:active 1:bias 0 0 0 0 0 14 evr16 data 0:off 1:on 0 0 0 0 0 13 evr8 data 0:off 1:on 0 0 0 0 0 12 evr4 data 0:off 1:on 0 0 0 0 0 11 evr2 data 0:off 1:on 0 0 0 0 0 10 evr1 data 0:off 1:on 0 0 0 0 0 9 spk p sw 0:on 1:off 1 1 1 1 1 8 line mute 0:off 1:on 1 1 1 1 1 7 line p sw 0:on 1:off 1 1 1 1 1 6 rec p sw 0:on 1:off 0 0 0 0 0 5 lpf trap 0:16khz 1:8khz 1 1 1 1 1 4 rec /pb sw 0:pb 1:rec 1 1 1 1 1 3 alc p sw 0:on 1:off 0 0 0 0 0 2 mic p sw 0:on 1:off 0 0 0 0 0 1 vref charging sw 0:off 1:on 0 0 0 0 0 serial control setting 0 line mute tr. 0:off 1:on 0 0 0 0 0 standby pin voltage applied to pin 3 3.3v 3.3v 3.3v 3.3v 3.3v major conditions (for the serial control setting, see the table in the right) 400 to 20khz lpf used, sw17=a 400 to 20khz lpf used, sw17=a thd: from 2nd to 5th harmonic jis-a filter used, sw17=b 400 to 20khz lpf used, sw17=a pin 17 level at which pin 16 becomes thd = 3% (from 2nd to 5th harmonic) pin 18 measurement of output voltage (under 6.2k load) sw18=on output pin t16 t16 t16 t16 t18 conditions v in =-36dbv f=1khz v in =-36dbv f=1khz no input f=1khz no input input pin t17 t17 t17 t17 t17 symbol vgmic hdmic vnomic vinmmx vmic no. mic output system 28 29 30 31 32
la74308lp no.a0898-10/16 description of pin functions pin no. pin description 1 speaker input 2 evr output 3 standby control 4 line output 5 line mute tr. output 6 c.s. input 7 clock input 8 data input 9 gnd 10 pb input 11 v cc a 12 rec output 13 alc detection 14 alc input 15 2nd order hpf 16 mic output 17 mic input 18 int power supply for mic 19 ripple rejection for vrefl 20 spk gnd 21 speaker positive-phase output 22 v cc sp 23 speaker negative-phase output 24 spk gnd
la74308lp no.a0898-11/16 block diagram spk gnd data t7 (clock) t6 c.s t12 rec out v cc sp t22 3.3v 0.1 alc in t11 v cc a 6.2k + 4.7 mic out a b t3 standby ctl rg=1k vref ba rg=1k 0.1 r r p p rec:50k /pb:200k + 0.1 22k 2k 10 sw10 + sw14 sw17 + 1 600 mute ctl lpf
la74308lp no.a0898-12/16 lpf characteristics evr characteristics spk output level & distortion rate la74308lp lpf characteristics -1.00e+02 -8.00e+01 -6.00e+01 -4.00e+01 -2.00e+01 0.00e+00 2.00e+01 1.00e+02 1.00e+03 1.00e+04 1.00e+05 frequency [h z] response [db] fs=8kh z mode fs=16khz mode la74308lp evr characteristics (at pb in reference input = -9dbv) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 5 10 15 20 25 30 35 5-bit data (decimal) gain [ db ] la74308lp spk output & th d characteristics (pb in max input -9dbv) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 5 10 15 20 25 30 35 5-bit data (decimal) spk8 output [ w ] 0 2 4 6 8 10 12 14 thd: from 2nd to 5th harmonic [ % ] spk outp ut thd
la74308lp no.a0898-13/16 la74308lp input/output pattern table pin pin name dc voltage ac voltage description of functions equivalent circuit diagram in pin 1 sp in 1.27v at pb reference input output level = -9dbv (evr max) speaker input pin 23 spk out- 1.27v at pb reference input output level = -9dbv (evr max) speaker negative-phase output pin 2 evr out 1.5v evr output pin 3 standby l standby control pin 2v or more: standby canceled 4 line out line output pin 5 line mute 1.5v at pb reference input output level = -9dbv line output mute transistor 6 7 8 cs clock data cs input pin clock input pin data input pin continued on next page. 400 11k 23 v cc sp(=3.3v) 1 10k 35k 2 12.5k vrefl v cc (=3.0v) 3 70k 50k 4 v cc (=3.0v) 26k vrefl 2k 14k 5 10 60k 6 7 8 50k
la74308lp no.a0898-14/16 continued from preceding page. pin pin name dc voltage ac voltage description of functions equivalent circuit diagram in pin 9 gnd 0v gnd pin 10 pb in 1.5v reference input level =-17dbv pb input pin 11 v cc 3v power supply pin 12 rec out 1.5v reference input level =-9dbv r output pin 13 alc det alc detection pin alc in (rec) 1.5v reference input level =-53dbv max input level =-8dbv alc input pin 14 evr in (pb) 1.5v evr input pin 15 hpf 1.5v used when forming the 2nd order hpf continued on next page. 1k 500 v cc (=3.0v) 13 500 vref rec:50k v cc (=3.0v) 14 pb:200k 100k v cc (=3.0v) 15 v cc (=3.0v) 10 500 49.5k v cc (=3.0v) vref 500 11k 6k 12
la74308lp no.a0898-15/16 continued from preceding page. pin pin name dc voltage ac voltage description of functions equivalent circuit diagram in pin mic out (rec) mic output pin (for rec mode) 16 lpf out (pb) 1.5v lpf output pin (for pb mode) 17 mic in 1.5v reference input level =-70dbv max input level =-25dbv mic input pin 18 mic v cc 2.30v mic power pin 19 vrefl 2.30v mic v cc and vrefl ripple rejection pin 20 24 sp gnd 0v speaker gnd pin 21 spk out+ 1.27v at pb reference input output level = -9dbv (evr max) speaker positive-phase output pin 22 v cc sp 3.3v speaker power pin vrefl 500 70k v cc (=3.0v) 17 10k 10.7k 21 23 v cc sp(=3.3v) v cc (=3.0v) 2.2k 28k 18 500 v cc (=3.0v) 16 v cc (=3.0v) 500 200k 400 19
la74308lp no.a0898-16/16 application circuit ps 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 alc mute + - + - evr logic mic v cc vref det vref charging circuit lpf 2.2k beep in stand-by low v cc sp 3.3v spk 8 mic in line out rec out pb in v cc a 3.0v data clock c. s. mute ctl r r p p rec: 50k / pb: 200k 0.1 sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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